The present invention relates generally to a semiconductor memory device, and more particularly to a sense amplifier performing a negative drive, a driving method of the sense amplifier performing a pull-down drive by a negative voltage, and a semiconductor memory device having the sense amplifier.
The data to be stored in a cell array or the data stored in the cell array is carried on a bit line of the semiconductor memory device. The data delivered between the bit line and a data bus is sensed and amplified by a sense amplifier.
The structure of a cross-coupled latch-type sense amplifier is shown in FIG. 1a. FIG. 1B shows the threshold voltage offset characteristic of a NMOS transistor and a PMOS transistor provided in the sense amplifier of FIG. 1a. 
In FIG. 1b, the X-axis indicates the threshold voltage value Vt of the NMOS transistor and the PMOS transistor located on the right-side of the sense amplifier shown in FIG. 1a. The Y axis indicates the threshold voltage value Vt of the NMOS transistor and the PMOS transistor located on the left-side of the sense amplifier shown in FIG. 1a. FIG. 1b shows a threshold voltage characteristic wherein the threshold voltage value measured for the NMOS transistors and PMOS transistors of multiple sense amplifiers is displayed on a coordinate point.
Referring to FIG. 1b, the NMOS transistors display a uniform distribution of threshold voltage values, while the PMOS transistors display a nonuniform distribution of threshold voltage values since a threshold voltage characteristic is distributed.
As previously stated, FIG. 1a shows the sense amplifier which senses and amplifies a voltage on the bit line associated with a cell array. FIG. 2 shows an operational timing diagram of the sense amplifier.
Referring to FIG. 2, in a precharge section, the bit lines BL, /BL and sense amplifier driving signals SAP, SAN have a bit line precharge voltage VBLP. The bit line precharge voltage VBLP is defined as ½ of the power supply voltage VDD, which is the high voltage of the cell.
In the charge share section, the word line WL is activated with the high voltage VPP so that the data of the cell is carried on the bit line BL.
In the sense amplifying section, in order to amplify the signal of the bit lines BL, /BL, the pull-down driving signal SAN transits to a ground voltage, and the pull-up driving signal SAP transits to the power supply voltage VDD. Therefore, the bit lines BL, /BL are amplified to the power supply voltage VDD and the ground voltage respectively.
In the restore section, the amplified signals on the bit lines BL, /BL are rewritten in the cell. Upon completion of restoring the data, the sense amplifying circuit 24 is returned to the precharge state.
The symbol SN is a storage node voltage and the symbol REF is a reference voltage applied to the bit line /BL if the data is carried on the bit line BL.
However, the semiconductor memory device described above causes the margin of the operation voltage for the threshold voltage to be reduced if the operation voltage is lowered, thereby deteriorating the operational characteristics of the sense amplifier.
Particularly, the threshed voltage difference between the PMOS transistors of the sense amplifier is larger than the threshold voltage difference between the NMOS transistors of the sense amplifier, as is shown in FIG. 1b. Therefore, the offset voltage amplified by the PMOS transistor is considerably larger than the offset voltage amplified by the NMOS transistor.
In the above described sense amplifier having the threshold voltage distribution characteristic shown in FIG. 1b, since the amplification driving capability is reduced if the operation voltage is lowered, the difference between the offset voltages becomes an important factor which influences the driving capability of the sense amplifier as the operation voltage is lowered.
Typically, the sense amplifier uses a voltage larger than the high voltage on the bit line in an overdrive manner in order to improve the driving capability of the PMOS transistor. However, a problem occurs which causes a data error in the output of the sense amplifier due to the great influence of the offset characteristic of the PMOS transistor.